Northwest-AI-Hub

CXR Pilot Run

Call for Pilot Run Participation - Deadline: March 1, 2025 

Participant Questionnaire (submit by March 1, 2025)
Frequently Asked Questions (FAQ) [PDF]

We are soliciting Users to participate in a pilot run that will serve as a demonstration of end-to-end CXR to the U.S. high tech community. We seek to build a first cohort of ten users to join in a single, Hub-funded CMOS run at the 40 nm technology scale to be processed at TSMC on 300 mm wafers. In addition, we will enable support to post-CMOS processing, namely downsizing the samples to smaller wafers or coupons, including cutting, backgrinding, beveling, and pad opening, as per User specifications. Samples will then be provided to Users for their own “+X” processing, packaging, and testing. The Hub facilities can be available to support some “+X” processing services, at User’s cost.

We also seek product and service providers interested in making their resources available to the CXR Users through our Hub.

What is CMOS+X? What is CXR? 

The Northwest AI Hub is the technology leaders in CMOS+X, a transformative, scalable approach to new device pathways. The basic pathway of CMOS+X consists of two parts – standard CMOS by leading foundries and “+X” processing done at the macro (metallization) level, where “X” may be RF/MS, FeFET, FeRAM, CNFET, RRAM/MRAM, gain cell memory, NEMS/MEMS, photonics, etc. More sophisticated pathways could enable the flexibility to add “X” devices available at transistor level or even augmentation of CMOS itself.

The mission of this Hub is to make these resources available to the U.S. high tech community through a new CXR business unit providing prototyping and development services for the heterogeneous integration of commercial foundry runs (CMOS) with emerging and advanced technologies (X), using a established design and process service Route (R). While our Hub has shown various CMOS+X pathways that use our member fab facilities and established partner/service providers, the CXR program aims to enable the basic and the most User friendly pathway to create a vibrant ecosystem of design, fabrication, and testing resources that is accessible to all U.S. based entities of interest.

Main Objective 

To establish CXR for the Microelectronics Commons to facilitate lab-to-fab for CMOS+X; “X”: RF/MS, FeFET, FeRAM, CNFET, RRAM/MRAM, gain cell memory, NEMS/MEMS, photonics, etc.

Pilot Objectives 

  • End-to-end CXR demo to pique interest and commitment from microelectronics community
  • Driver to stand up proper infrastructure of the Hub to support future CXR runs, including concierge service to the Users in design and integration and post-CMOS processing for sample preparation to enable subsequent “+X” processing 

Pilot Plan 

  • Seek cohort of 10 Users for TSMC 40 nm CMOS run on 300 mm wafers (Hub funded) with the concierge service to help Users in design and integration if needed (supported by the Hub at cost)
  • Seek vendors as Hub members to provide critical capabilities as a part of infrastructure for the CXR support
  • Stand up post-CMOS processing to produce wafers (e.g. 100 – 200 mm) or coupons (e.g. >1 cm x 1 cm) per User’s specification, including any necessary cutting, back-grinding and beveling and pad opening (supported by the Hub at cost)
  • User funded “+X” processing, packaging and testing